Working with the CMOS inverter approximate switching time equation. Attachments in Word.

The circuit shown in Figure B2 is of a CMOS inverter driving a capacitive load. VDD represents logic level "1" and zero volts logic level "0".   M1 is an nMOS device and M2 is a pMOS device.

(a) Calculate the approximate switching time that is obtained if the output is loaded by a capacitance, CL , of 0.2 pF due to interconnections and the inputs of other gates.
(b) Explain what would happen to the switching time if the lateral dimensions of the circuit are reduced by a factor of two whilst the vertical dimensions and all other parameters of the transistors remain unaltered.