CMOS inverter

Consider a CMOS inverter biased at Vdd=4V and assume the transistors are matched with Kn=Kn and Vtn=-Vtp=/2*Vdd. Derive the expression for, and calculate the noise margins. Please see attached files.

{10.11} Electric circuits problem

Please open attached pdf file for question and diagram. Explain why the final solution is a positive or a negative sign. Please show how you arrived at your answer with step by step method. The given answers are verified and correct. To OTA: Please take this question only if you can match one of the given answers. Thank you.

Comment on Frankenstein power supply

Hi. I've attached a circuit diagram. The schematic is for a dc power supply. It's purpose it to charge nicad batteries. However, we are having trouble locating the transformer. The transformer has been omitted, and the power is just represented by an AC power source. I'm a little unclear about the C-L-C portion of the circuit (Pi network?), the purpose of the transistor, and how the zener diode is operating in its current position. If you could spend a little time, please walk me through how the current and voltage are changing through these portions of the circuit, how the filtering is working, how the ripple is being affected, and how the voltage is being regulated. Also, i... click for more

Two power sources in a circuit

I need to find the voltmeter reading and how to deal with 2 power sources Is this going into Thevenins or kirchoffs?

Derive rationalised admittance expressions

This question is part of my revision guide, it is worth 15 marks, I am unsure of what the question is asking me to do. Could you please derive the expression in detail and show me why it would be worth so many marks as a question.