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· 41-45 · 46-50 · 51-55 · 56-60 · 61-65 · 66-70 · 71-75 · 76-80 · 81-85 · 86-90 · 91-95 ·code spatial and temporal locality
What would be examples of spatial and temporal locality in the following code: for (i = 0; i < 20; i++) for(j=0; j<10;j++ a[i] =a[i]*j
Subject:
Computer Science
Topic:
Computer Architecture
Posting ID:
145893
OTA ID:
103987
Compute the cost of main and cache memories and hit ratio.
Explain the meaning of Tc, Cc, Tm and Cm in the following memory system specification. Tc = 100 ns Cc = 10^(-4) $/bit Tm = 1200 ns Cm = 10^(-4) $/bit a. Calculate the cost of 1 MByte of main memory using the above parameters. b. What is the cost of 1 MByte of cache memory? c. If the effective access time is 10% greater than the cache access time, what would be the hit ratio (H)?
Subject:
Computer Science
Topic:
Computer Architecture
Posting ID:
145900
OTA ID:
105381
A single level cache has following specifications. Access time = 2.5 ns Line size = 64 bytes Hit ratio = 0.95 Main memory uses a block transfer capability, and has first word (4 bytes) access time of 50 ns and access time for following words as 5 ns. Compute the access time when there is a cache miss? Assume that the cache waits until the line has been fetched from main memory and then re-executes for a hit. Will increasing the line size to 128 bytes, and a resulting increase in H (hit ratio) to .97, reduce the average memory access time?
Subject:
Computer Science
Topic:
Computer Architecture
Posting ID:
145903
OTA ID:
105381
Compute the main memory address format from the data given about cache and main memory.
Given that a system has 2-way set associative cache of size 8 KBytes, with 16 bytes cache lines, and a byte-addressable main memory of size 64 MBytes. What is the format of main memory address?
Subject:
Computer Science
Topic:
Computer Architecture
Posting ID:
145906
OTA ID:
105381
A microcomputer memory is built from 64K X 1 DRAM, with DRAM cell array organized into 256 rows. Each row needs to be refreshed at least once every 4 ms, strictly on a periodic basis. 1. Give time period between successive refresh requests. 2. How long a refresh address counter do we need?
Subject:
Computer Science
Topic:
Computer Architecture
Posting ID:
146196
OTA ID:
105381
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