Input/Output Organization

The address bus of a computer has 16 address lines, A15_0 If the address assigned to one device is 7CA416 and the address decoder for that device ignores lines A8 and A9, what are all the addresses to which this device will respond?

The Memory System

Criticize the following statement: "Using a faster processor chip results in a corresponding increase in performance of a computer even if the main memory speed remains the same."

Digital Logic

What is the meaning of having 2 lines forking from say input A going into a gate? A ______ __________| | |_____| | B ________| | |______| A _______ __________| | | | __________| | B |______|

Compute the main memory address format for the given memory configuration.

Given a word addressable machine, with following memory configuration. - 64 cache lines divided into 4 sets. - main memory contains 4K blocks of 128 words each. How does the main memory address format look?

Compute the memory address format for a byte addressable main memory using direct mapped cache, and solve related numerical problems.

Given, a byte addressable main memory of 2^16 bytes and block size of 8 bytes, using direct mapped cache consisting of 32 lines. a. How many total memory bytes can be stored in the cache? b. How is a 16 bit memory address divided into tag, line number and byte number? c. Into what line would byte with the following address be stored? 0001 0001 0001 1011